SH7047 Datasheet, PDF (605/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

19.8 Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase the flash memory in on-
board programming modes. Depending on the FLMCR1 and FLMCR2 settings, the flash memory
operates in one of the following four modes: Program mode, program-verify mode, erase mode,
and erase-verify mode. The programming control program in boot mode and the user
program/erase control program in user program mode use these operating modes in combination to
perform programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 19.8.1, Program/Program-Verify Mode and section
19.8.2, Erase/Erase-Verify Mode, respectively.
19.8.1 Program/Program-Verify Mode
When writing data or programs to the flash memory, the program/program-verify flowchart shown
in Figure 19.9 should be followed. Performing programming operations according to this
flowchart will enable data or programs to be written to the flash memory without subjecting the
chip to voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
programming has already been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128-
byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation and additional programming data computation according to
Figure 19.9.
4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
5. The time during which the P bit is set to 1 is the programming time. Figure 19.9 shows the
allowable programming time.
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
An overflow cycle of approximately 6.6 ms is allowed.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address to be read. Verify
data can be read in longwords from the address to which a dummy write was performed.
8. The number of repetitions of the program/program-verify sequence to the same bit should not
exceed the maximum number of programming (N).
Rev. 2.00, 09/04, page 565 of 720