SH7047 Datasheet, PDF (684/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

25.3.14 AUD Timing
Table 25.16 shows AUD timing.
Table 25.16 AUD Timing
Conditions: V_CC = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to
+75°C (Standard product)*, T_a = –40°C to +85°C (Wide temperature-range product)*
Item
Symbol Min
Max
Unit Figures
AUDRST pulse width (Branch trace)
AUDRST pulse width (RAM monitor)
AUDMD setup time (Branch trace)
AUDMD setup time (RAM monitor)
Branch trace clock cycle
Branch trace clock duty
Branch trace data delay time
Branch trace data hold time
Branch trace SYNC delay time
Branch trace SYNC hold time
RAM monitor clock cycle
RAM monitor clock low pulse width
RAM monitor output data delay time
RAM monitor output data hold time
RAM monitor input data setup time
RAM monitor input data hold time
RAM monitor SYNC setup time
RAM monitor SYNC hold time
Load conditions: AUDCK (output):
AUDSYNC:
t_AUDRSTW
20
t_AUDRSTW
5
t
20
AUDMDS
t
5
AUDMDS
t
2
BTCYC
t
40
BTCKW
t_BTDD
—
t_BTDH
0
t_BTSD
—
t_BTSH
0
t_RMCYC
80
t
35
RMCKW
t
7
RMDD
t
5
RMDHD
t
30
RMDS
t_RMDH
5
t_RMSS
20
t_RMSH
5
CL = 30 pF
CL = 100 pF
—
—
—
—
2
60
30
—
30
—
—
—
t -20
RMCYC
—
—
—
—
—
t_cyc
t_RMCYC
t
cyc
t
RMCYC
t
cyc
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
25.26
Figure
25.27
Figure
25.28
AUDATA3 to AUDATA0: CL = 100 pF
Note: * See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
Rev. 2.00, 09/04, page 644 of 720