SH7047 Datasheet, PDF (650/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

MSTCR2
Initial
Bit Bit Name Value R/W
15 
1
R/W
14 MSTP14 1
R/W
13 MSTP13 1
R/W
12 MSTP12 1
R/W
11 
0
R
10 
0
R/W
Description
Reserved
This bit is always read as 1, and should always be
written with 1.
Motor management timer (MMT)
Multi-function timer pulse unit (MTU)
Compare match timer (CMT)
Reserved
These bits are always read as 0, and should always be
written with 0.
9 MSTP9 0
8
0
7, 6 
All 1
5 MSTP5 1
4 MSTP4 1
R/W Renesas controller area network 2 (HCAN2)
R/W Reserved
This bit is always read as 0, and should always be
written with 0.
R/W Reserved
This bit is always read as 1, and should always be
written with 1.
R/W A/D converter (A/D1)
R/W A/D converter (A/D0)
3
MSTP3
0
R/W Advanced user debugger (AUD)*
2
MSTP2
0
R/W Renesas user debug interface (H-UDI)*
1
0
R
Reserved
This bit is always read as 0, and should always be
written with 0.
0 MSTP0 0
R/W User break controller (UBC)
Note: * In E10A debugging mode (when DBGMD = low-level input), although this bit can be
read and written, AUD and H-UDI are always operated regardless of set values.
Rev. 2.00, 09/04, page 610 of 720