SH7047 Datasheet, PDF (669/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

25.3.4 Bus Timing
Table 25.6 shows bus timing.
Table 25.6 Bus Timing
Conditions: V_CC = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to
+75°C (Standard product)* ¹, T_a = –40°C to +85°C (Wide temperature-range
product)*¹.
Item
Symbol Min
Typ
Max Unit Figures
Address delay time
CS delay time 1
t_AD
—
22
30
ns
Figures 25.10,
t
—
22
35
ns
25.11
CSD1
CS delay time 2
t
—
15
35
ns
CSD2
Read strobe delay time 1 t
—
20
35
ns
RSD1
Read strobe delay time 2 t_RSD2
—
15
35
ns
Read data setup time
t_RDS
15
—
—
ns
Read data hold time
t_RDH
0
—
—
ns
Write strobe delay time 1
t_WSD1
—
20
30
ns
Write strobe delay time 2
t_WSD2
—
15
30
ns
Write data delay time
t
—
—
30
ns
WDD
Write data hold time
t
0
WDH
—
—
ns
WAIT setup time
t
15
—
—
ns
Figure 25.12
WTS
WAIT hold time
t
0
WTH
—
—
ns
Read data access time
t_ACC
t_CYC×
—
(2+n)-
35*²*³
—
ns
Figures 25.10,
25.11
Access time from read
t_OE
strobe
t_CYC×
—
—
ns
(1.5+n)-
33*²
Write address setup time t
AS
0*⁴
—
—
ns
Write address hold time
t
WR
5*⁵
—
—
ns
Write data hold time
t
WRH
0*⁴
—
—
ns
Notes: 1. See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
2. n is the number of wait cycles.
3. At the CS assert period extension, t × (3 + n) - 35.
CYC
4. At the CS assert period extension, t_CYC.
5. At the CS assert period extension, 5 + t_CYC.
Rev. 2.00, 09/04, page 629 of 720