SH7047 Datasheet, PDF (297/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10.68 shows the
timing for status flag clearing by the CPU, and Figure 10.69 shows the timing for status flag
clearing by the DTC.
TSR write cycle
T1
T2
Pφ
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 10.68 Timing for Status Flag Clearing by the CPU
Pφ
Address
Status flag
DTC
read cycle
T1
T2
DTC
write cycle
T1
T2
Source address
Destination
address
Interrupt
request signal
Figure 10.69 Timing for Status Flag Clearing by DTC Activation
Rev. 2.00, 09/04, page 257 of 720