SH7047 Datasheet, PDF (413/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.19 shows a sample
flowchart for serial data reception.
Initialization
[1] SCI initialization:
[1]
Set the RxD pin using the PFC.
Start reception
[2] [3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
Read ORER flag in SSR
[2]
performing the appropriate error
processing, clear the ORER flag to 0.
Transfer cannot be resumed if the
ORER = 1
Yes
[3]
ORER flag is set to 1.
[4] SCI status check and receive data
No
Error processing
read:
Read SSR and check that the RDRF
(Continued below)
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
Read RDRF flag in SSR
[4]
to 0.
Transition of the RDRF flag from 0 to 1
No
RDRF = 1
can also be identified by an RXI
interrupt.
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
[5]
Yes
[5] Serial reception continuation
procedure:
To continue serial reception, before
the MSB (bit 7) of the current frame is
received, reading the RDRF flag,
reading RDR, and clearing the RDRF
flag to 0 should be finished. The
RDRF flag is cleared automatically
when the DTC is activated by a
receive data full interrupt (RXI) request
and the RDR value is read.
Clear RE bit in SCR to 0
<End>
[3]
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
<End>
Figure 12.19 Sample Serial Reception Flowchart
Rev. 2.00, 09/04, page 373 of 720