SH7047 Datasheet, PDF (666/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

25.3.3 Control Signal Timing
Table 25.5 shows control signal timing.
Table 25.5 Control Signal Timing
Conditions: V_CC = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to
+75°C (Standard product)*¹, T_a = –40°C to +85°C (Wide temperature-range
product)*¹.
Item
Symbol Min Max Unit Figures
RES rise time, fall time
t , t _{RESr RESf}
—
200
ns
Figure 25.5
RES pulse width
t
RESW
25
—
t
Figure 25.6
cyc
RES setup time
t
RESS
25
—
ns
MRES pulse width
t
20
—
t
MRESW
cyc
MRES setup time
t_MRESS
19
—
ns
MD3 to MD0 setup time
t_MDS
20
—
t_cyc
NMI rise time, fall time
t , t _{NMIr NMIIf}
—
200 ns
NMI setup time
t_NMIS
19
—
ns
Figure 25.7
IRQ3 to IRQ0 setup time*² (edge detection) t_IRQES
19
—
ns
IRQ3 to IRQ0 setup time*² (level detection)
t
IRQLS
19
—
ns
NMI hold time
t
19
—
ns
NMIH
IRQ3 to IRQ0 hold time
t
IRQEH
19
—
ns
IRQOUT output delay time
t
IRQOD
—
100
ns
Figure 25.8
Bus request setup time
t_BRQS
19
—
ns
Figure 25.9
Bus acknowledge delay time 1
t_BACKD1
—
30
ns
Bus acknowledge delay time 2
t_BACKD2
—
30
ns
Bus three-state delay time
t_BZD
—
30
ns
Notes: 1. See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
2. The RES, MRES, NMI and IRQ3 to IRQ0 signals are asynchronous inputs, but when
the setup times shown here are observed, the signals are considered to have been
changed at clock rise (RES, MRES) or fall (NMI and IRQ3 to IRQ0). If the setup times
are not observed, the recognition of these signals may be delayed until the next clock
rise or fall.
Rev. 2.00, 09/04, page 626 of 720