SH7047 Datasheet, PDF (495/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

15.3.18 Timer Control Register (TCR)
TCR is a 16-bit readable/writable register that controls the timer operation. This register performs
all the settings of periodic transmit condition and restriction. This register should be set before
starting timer operation.
Initial
Bit Bit Name Value R/W Description
15
TCR15
0
R/W Enable Timer
Controls on/off of the timer.
0: Timer stops running
14
TCR14
0
1: Timer starts running
Notes: 1. The timer does not stop running immediately
after this bit is cleared to 0. The timer stops
running after an overflow or compare match
occurred.
2. The timer malfunctions in this LSI. To
prevent the timer from running, the write
value to this bit should always be 0.
R/W Disable ICR0
Controls whether to enable or disable the input capture
register 0 (ICR0). When this bit is set to 1, the timer
value is always captured every time a StartOfFrame
(SOF) appears on the CAN bus, regardless of whether
the HCAN2 is a transmitter or receiver. When this bit is
cleared to 0, the ICR0 value remains latched.
0: ICR0 is disabled
1: ICR0 is enabled and captures the timer value at every
SOF
[Clearing condition]
• CAN-ID of the receive message = mailbox with CCM
set (when TCR9 = 1)
13
TCR13
0
R/W Timestamp Control for Reception
Specifies if the timestamp of each mailbox is recorded at
the start of frame (SOF) or end of frame (EOF). Selects
ICR1 which becomes a trigger of the timestamp for
operation in reception.
0: Timestamp is recorded at every SOF
1: Timestamp is recorded at every EOF
Note:
In this LSI, timestamp is not recorded at every
SOF. When using the timestamp in reception,
write 1 to this bit.
Rev. 2.00, 09/04, page 455 of 720