SH7047 Datasheet, PDF (427/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

13.4 Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes; single mode and scan mode. There are two kinds of scan mode: continuous
mode and single-cycle mode. When changing the operating mode or analog input channel, in order
to prevent incorrect operation, first clear the ADST bit to 0 in ADCR. The ADST bit can be set at
the same time when the operating mode or analog input channel is changed.
13.4.1 Single Mode
In single mode, A/D conversion is to be performed only once on the specified single channel. The
operations are as follows.
1. A/D conversion is started when the ADST bit in ADCR is set to 1, according to software,
MTU, MMT, or external trigger input.
2. When A/D conversion is completed, the result is transferred to the A/D data register
corresponding to the channel.
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST
bit is automatically cleared to 0 and the A/D converter enters the idle state.
When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D
converter enters the idle state.
13.4.2 Continuous Scan Mode
In continuous scan mode, A/D conversion is to be performed sequentially on the specified
channels (eight channels maximum). The operations are as follows.
1. When the ADST bit in ADCR is set to 1 by software, MTU, MMT, or external trigger input,
A/D conversion starts on the channel with the lowest number in the group (AN0, AN1, ...,
AN3).
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the A/D data register corresponding to each channel.
3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends.
Conversion of the first channel in the group starts again.
4. Steps 2 to 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops and the A/D converter enters the idle state.
Rev. 2.00, 09/04, page 387 of 720