SH7047 Datasheet, PDF (640/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Bus error conditions are shown below.
1. Word access to address 4n+1 or 4n+3
2. Longword access to address 4n+1, 4n+2, or 4n+3
3. Longword access to on-chip I/O 8-bit area
4. Access the HCAN2 area in longwords
5. Access to external area in single-chip mode
Table 23.2 Ready Flag Format
Bit 3
Fixed at 0
Bit 2
0: Normal status
1: Bus error
Bit 1
0: Normal status
1: Command error
Bit 0
0: Not ready
1: Ready
AUDCK
AUDSYNC
AUDATAn
AUDCK
AUDSYNC
AUDATAn
0000 1000 A3 to A0
DIR
Input
Input/output changeover
A31 to A28
0000
Not ready
0001
Ready
0001 0001 D3 to D0 D7 to D4
Ready Ready
Output
Figure 23.5 Example of Read Operation (Byte Read)
0000 1110 A3 to A0
DIR
Input/output changeover
A31 to A28 D3 to D0
D31 to D28
0000
Not ready
Input
0001
Ready
Output
0001 0001
Ready Ready
Figure 23.6 Example of Write Operation (Longword Write)
AUDCK
AUDSYNC
AUDATAn
0000 1010 A3 to A0
DIR
Input
Input/output changeover
A31 to A28
0000
Not ready
0101
Ready
(Bus error)
0101 0101
Ready Ready
(Bus error) (Bus error)
Output
Figure 23.7 Example of Error Occurrence (Longword Read)
Rev. 2.00, 09/04, page 600 of 720