SH7047 Datasheet, PDF (70/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Operation
Classification Types Code
Function
Arithmetic
operations
SUBC
SUBV
Binary subtraction with borrow
Binary subtraction with underflow
Logic
6
operations
AND
NOT
Logical AND
Bit inversion
OR
Logical OR
TAS
Memory test and bit set
TST
Logical AND and T bit set
XOR
Exclusive OR
Shift
10
ROTL
One-bit left rotation
ROTR
One-bit right rotation
ROTCL One-bit left rotation with T bit
ROTCR One-bit right rotation with T bit
SHAL
One-bit arithmetic left shift
SHAR
One-bit arithmetic right shift
SHLL
One-bit logical left shift
SHLLn n-bit logical left shift
SHLR
One-bit logical right shift
SHLRn n-bit logical right shift
Branch
9
BF
Conditional branch, conditional branch with
delay (Branch when T = 0)
BT
Conditional branch, conditional branch with
delay (Branch when T = 1)
BRA
Unconditional branch
BRAF
Unconditional branch
BSR
Branch to subroutine procedure
BSRF
Branch to subroutine procedure
JMP
Unconditional branch
JSR
Branch to subroutine procedure
RTS
Return from subroutine procedure
No. of
Instructions
14
14
11
Rev. 2.00, 09/04, page 30 of 720