SH7047 Datasheet, PDF (597/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

19.5.2 Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing.
Initial
Bit Bit Name Value R/W
7
FLER
0
R
6 to 0 
All 0
R
Description
Indicates that an error has occurred during an operation
on flash memory (programming or erasing). When flash
memory goes to the error-protection state, FLER is set to
1.
See section 19.9.3, Error Protection, for details.
Reserved
These bits are always read as 0.
19.5.3 Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase block. EBR1 is initialized to H'00 when a high level is
input to the FWP pin. It is also initialized to H'00, when the SWE bit in FLMCR1 is 0 regardless
of value in the FWP pin. Do not set more than one bit at a time in EBR1 and EBR2, as this will
cause all the bits in EBR1 and EBR2 to be automatically cleared to 0.
Initial
Bit Bit Name Value R/W
7
EB7
0
R/W
6
EB6
0
R/W
5
EB5
0
R/W
4
EB4
0
R/W
3
EB3
0
R/W
2
EB2
0
R/W
1
EB1
0
R/W
0
EB0
0
R/W
Description
When this bit is set to 1, 4 kbytes of EB7 (H'007000 to
H'007FFF) are to be erased.
When this bit is set to 1, 4 kbytes of EB6 (H'006000 to
H'006FFF) are to be erased.
When this bit is set to 1, 4 kbytes of EB5 (H'005000 to
H'005FFF) are to be erased.
When this bit is set to 1, 4 kbytes of EB4 (H'004000 to
H'004FFF) are to be erased.
When this bit is set to 1, 4 kbytes of EB3 (H'003000 to
H'003FFF) are to be erased.
When this bit is set to 1, 4 kbytes of EB2 (H'002000 to
H'002FFF) are to be erased.
When this bit is set to 1, 4 kbytes of EB1 (H'001000 to
H'001FFF) are to be erased.
When this bit is set to 1, 4 kbytes of EB0 (H'000000 to
H'000FFF) are to be erased.
Rev. 2.00, 09/04, page 557 of 720