SH7047 Datasheet, PDF (533/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Count Operation: Set 2Td (Td: value set in TDDR) as the initial value of the TCNT counter
when CST bit in TCNR is set to 0.
When the CST bit is set to 1, TCNT counts up to {value set in TPBR + 2Td}, and then starts
counting down. When TCNT reaches 2Td, it starts counting up again, and continues in this way.
TCNT is constantly compared with TGRU, TGRV, and TGRW. In addition, it is compared with
TGRUU, TGRVU, TGRWU, and TPDR when counting up, and with TGRUD, TGRVD,
TGRWD, and 2Td when counting down.
TDCNT0 to TDCNT5 are read-only counters. It is not necessary to set their initial values.
TDCNT0, TDCNT2, and TDCNT4 start counting up at the falling edge of a positive phase
compare match output when TCNT is counting down. When they become equal to TDDR they are
cleared to 0 and halt.
TDCNT1, TDCNT3, and TDCNT5 start counting up at the falling edge of a negative phase
compare match output when TCNT is counting up. When they match TDDR they are cleared to 0
and halt.
TDCNT0 to TDCNT5 are compared with TDDR only while a count operation is in progress. No
count operation is performed when the TDDR value is 0.
Figure 16.3 shows an example of the TCNT count operation.
H'FFFF
TPDR
TGRUU
Td
TGRU
TGRUD
2Td
TCNT
1/2 period
Td
(TPBR)
2Td
H'0000
2Td
Td
Figure 16.3 Example of TCNT Count Operation
Rev. 2.00, 09/04, page 493 of 720