SH7047 Datasheet, PDF (546/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Pφ
Address
Buffer register
write cycle
T1 T2
Buffer register
address
Write signal
Compare match
signal
Interrupt request
signal
Buffer register
Buffer register write data
N
M
Compare register
M
Figure 16.15 Contention between Buffer Register Write and Compare Match
Contention between Compare Register Write and Compare Match: If a compare match
occurs in the T2 state of a compare register (TGR or TPDR) write cycle, the compare register
write is not performed, and data is transferred from the buffer register (TBRU, TBRV, TBRW, or
TPBR) to the compare register by a buffer operation.
Figure 16.16 shows the timing in this case.
Rev. 2.00, 09/04, page 506 of 720