SH7047 Datasheet, PDF (482/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

15.3.14 Mailbox Interrupt Mask Registers (MBIMR1, MBIMR0)
MBIMR1 and MBIMR0 are 16-bit registers that enable individual mailbox interrupt requests.
• MBIMR1
Bit Bit Name
15 MBIMR31
14 MBIMR30
13 MBIMR29
12 MBIMR28
11 MBIMR27
10 MBIMR26
9
MBIMR25
8
MBIMR24
7
MBIMR23
6
MBIMR22
5
MBIMR21
4
MBIMR20
3
MBIMR19
2
MBIMR18
1
MBIMR17
0
MBIMR16
Initial Value R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Description
When MBIMRn (n = 16 to 31) is cleared to 0, the
interrupt request in mailbox n is enabled. When set
to 1, the interrupt request is masked.
The interrupt source in a transmit mailbox is TXPRn
(n = 16 to 31) clearing caused by transmission end
or transmission abort. The interrupt source in a
receive mailbox is RXPRn (n = 16 to 31) setting
caused by reception end.
0: Interrupt request in corresponding mailbox is
enabled
1: Interrupt request in corresponding mailbox is
disabled
Rev. 2.00, 09/04, page 442 of 720