SH7047 Datasheet, PDF (53/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Section 2 CPU
2.1 Features
• General-register architecture
 Sixteen 32-bit general registers
• Sixty-two basic instructions
• Eleven addressing modes
 Register direct [Rn]
 Register indirect [@Rn]
 Register indirect with post-increment [@Rn+]
 Register indirect with pre-decrement [@-Rn]
 Register indirect with displacement [@disp:4,Rn]
 Register indirect with index [@R0, Rn]
 GBR indirect with displacement [@disp:8,GBR]
 GBR indirect with index [@R0,GBR]
 Program-counter relative with displacement [@disp:8,PC]
 Program-counter relative [disp:8/disp:12/Rn]
 Immediate [#imm:8]
Rev. 2.00, 09/04, page 13 of 720