SH7047 Datasheet, PDF (310/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

10.7.15 Overflow Flags in Reset Sync PWM Mode
When set to reset sync PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of
TSTR is set to 1. At this point, TCNT_4’s count clock source and count edge obey the TCR_3
setting.
In reset sync PWM mode, with cycle register TGRA_3’s set value at H'FFFF, when specifying
TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF,
then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this
point, TSR’s overflow flag TCFV bit is not set.
Figure 10.82 shows a TCFV bit operation example in reset sync PWM mode with a set value for
cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without
synchronous setting for the counter clear source.
TGRA_3
(H'FFFF)
Counter cleared by compare match 3A
TCNT_3 = TCNT_4
H'0000
TCFV_3
TCFV_4
Not set
Not set
Figure 10.82 Reset Sync PWM Mode Overflow Flag
Rev. 2.00, 09/04, page 270 of 720