SH7047 Datasheet, PDF (184/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

9.6.3 CS Assert Period Extension
Idle cycles can be inserted to prevent extension of the RD or WRL signal assert period beyond the
length of the CS0 signal assert period by setting the SW0 bit of BCR2. This allows for flexible
interfaces with external circuitry. The timing is shown in figure 9.6. T_h and T_f cycles are added
respectively before and after the normal cycle. Only CS0 is asserted in these cycles; RD and WRL
signals are not. Further, data is extended up to the T_f cycle, which is effective for gate arrays and
the like, which have slower write operations.
Th
T1
T2
Tf
CK
Address
CS0
Read
RD
Data
Write
WRL
Data
Figure 9.6 CS Assert Period Extension Function
Rev. 2.00, 09/04, page 144 of 720