SH7047 Datasheet, PDF (192/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Input/output pins
Channel 3: TIOC3A
TIOC3B
TIOC3C
TIOC3D
Channel 4: TIOC4A
TIOC4B
TIOC4C
TIOC4D
Interrupt request signals
Channel 3: TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
Channel 4: TGI4A
TGI4B
TCI4C
TCI4D
TGI4V
Clock input
Internal clock: Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
External clock: TCLKA
TCLKB
TCLKC
TCLKD
Input/output pins
Channel 0: TIOC0A
TIOC0B
TIOC0C
TIOC0D
Channel 1: TIOC1A
TIOC1B
Channel 2: TIOC2A
TIOC2B
Internal data bus
A/D converter conversion
start signal
Interrupt request signals
Channel 0: TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1: TGI1A
TGI1B
TCI1V
TCI1U
Channel 2: TGI2A
TGI2B
TCI2V
TCI2U
[Legend]
TSTR:
Timer start register
TSYR:
Timer synchro register
TCR:
Timer control register
TMDR:
Timer mode register
TIOR (H, L): Timer I/O control registers (H, L)
TIER:
Timer interrupt enable register
TSR:
Timer status register
TCNT:
Timer counter
TGR (A, B, C, D): Timer general registers (A, B, C, D)
Figure 10.1 Block Diagram of MTU
Rev. 2.00, 09/04, page 152 of 720