SH7047 Datasheet, PDF (178/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

9.5 Description of Registers
9.5.1 Bus Control Register 1 (BCR1)
BCR1 is a 16-bit readable/writable register that enables access to the MMT and MTU control
registers and specifies the bus size of the CS0 space.
The AOSZ bit of BCR1 is written to during the initialization stage after a power-on reset. Do not
change the values thereafter. In on-chip ROM enabled mode, do not access any of the CS0 space
until completion of register initialization.
Initial
Bit
Bit Name Value
15

0
14
MMTRWE 1
13
MTURWE 1
12 to 8 
All 0
7 to 4 
All 0
3 to 1 
All 1
0
A0SZ
1
R/W Description
R
Reserved
This bit is always read as 0 and should always be
written with 0.
R/W MMT Read/Write Enable
This bit enables MMT control register access. For
details, refer to MMT section.
0: MMT control register access is disabled
1: MMT control register access is enabled
R/W MTU Read/Write Enable
This bit enables MTU control register access. For
details, refer to MTU section.
0: MTU control register access is disabled
1: MTU control register access is enabled
R
Reserved
These bits are always read as 0 and should always
be written with 0.
R
Reserved
These bits are always read as 0 and should always
be written with 0.
R
Reserved
These bits are always read as 1 and should always
be written with 1.
R/W In on-chip ROM enabled mode, 0 should be written to
this bit to specify a bus size of 8 bits before the CS0
space is accessed.
Note: In on-chip ROM disabled mode, the CS0
space bus size is specified by the mode pin.
Rev. 2.00, 09/04, page 138 of 720