SH7047 Datasheet, PDF (119/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

6.3.3 IRQ Status Register (ISR)
ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins
IRQ0 to IRQ3. When IRQ interrupts are set to edge detection, held interrupt requests can be
withdrawn by writing 0 to IRQnF after reading IRQnF = 1.
Bit
Bit Name
15 to 8 
Initial
Value
All 0
7
IRQ0F
0
6
IRQ1F
0
5
IRQ2F
0
4
IRQ3F
0
3 to 0 
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W IRQ0 to IRQ3 Flags
R/W These bits display the IRQ0 to IRQ3 interrupt request
R/W ^status.
R/W ^{[Setting condition]}
• When interrupt source that is selected by ICR1
and ICR2 has occurred.
[Clearing conditions]
• When 0 is written after reading IRQnF = 1
• When interrupt exception processing has been
executed at high level of IRQn input under the low
level detection mode.
• When IRQn interrupt exception processing has
been executed under the edge detection mode of
falling edge, rising edge or both of falling and
rising edge.
• When the DISEL bit of DTMR of DTC is 0, after
DTC has been started by IRQn interrupt.
R/W Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00, 09/04, page 79 of 720