SH7047 Datasheet, PDF (468/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value R/W Description
3
IMR3
1
R/W Transmit Error Warning Interrupt Mask
When this bit is cleared to 0, ERS1 (interrupt request by
IRR3) is enabled. When set to 1, ERS1 is masked.
2
IMR2
1
R/W Remote Frame Request Interrupt Mask
When this bit is cleared to 0, RM1 (interrupt request by
IRR2) is enabled. When set to 1, RM1 is masked.
1
IMR1
1
R/W Receive Message Interrupt Mask
When this bit is cleared to 0, RM1 (interrupt request by
IRR1) is enabled. When set to 1, RM1 is masked.
0
IMR0
1
R/W Reset/Halt/Sleep Interrupt Mask
When this bit is cleared to 0, OVR1 (interrupt request by
IRR0) is enabled. When set to 1, OVR1 is masked.
Rev. 2.00, 09/04, page 428 of 720