SH7047 Datasheet, PDF (579/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Table 18.1 Port A Data Register L (PADRL) Read/Write Operations
Bits 15 to 0:
PAIORL
0
1
Pin Function
General input
Other than
general input
General output
Other than
general output
Read
Write
Pin state
Can write to PADRL, but it has no effect on pin
state
Pin state
Can write to PADRL, but it has no effect on pin
state
PADRL value Value written is output from pin
PADRL value Can write to PADRL, but it has no effect on pin
state
18.2 Port B
Port B is an input/output port with the six pins shown in figure 18.2.
Port B
PB5 (I/O) / IRQ3 (input) / POE3 (input) / CK (output)
PB4 (I/O) / IRQ2 (input) / POE2 (input) / SCK4 (I/O)
PB3 (I/O) / IRQ1 (input) / POE1 (input) / TXD4 (output)
PB2 (I/O) / IRQ0 (input) / POE0 (input) / RXD4 (input)
PB1 (I/O) / A17 (output) / HRxD1 (input) / SCK4 (I/O)
PB0 (I/O) / A16 (output) / HTxD1 (output)
Figure 18.2 Port B
18.2.1 Register Descriptions
Port B is a 6-bit input/output port. Port B has the following register. For details on register
addresses and register states during each processing, refer to appendix A, Internal I/O Register.
• Port B data register (PBDR)
18.2.2 Port B Data Register (PBDR)
The port B data register (PBDR) is a 16-bit readable/writable register that stores port B data. Bits
PB5DR to PB0DR correspond to pins PB5 to PB0 (multiplexed functions omitted here).
When a pin functions is a general output, if a value is written to PBDR, that value is output
directly from the pin, and if PBDR is read, the register value is returned directly regardless of the
pin state.
Rev. 2.00, 09/04, page 539 of 720