SH7047 Datasheet, PDF (751/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Item
Page Revisions (See Manual for Details)
15.3.16 Mailboxes (MB0 448, Bits 15, 11, and 6 in the MBx[4] and MBx[5] registers:
to MB31)
450 _{Note added.}
449 Bits 13 in the MBx[4] and MBx[5] registers:
Description added.
452 Bits 15 to 0 in the MBx[6] register:
Description amended.
453 Note amended.
Note: * When MBC = B'001, B'010, B'100, and B'101,
these registers become a local acceptance filter
mask (LAFM) field.
15.3.18 Timer Control
Register (TCR)
455 to Description amended.
457
15.4.1 Hardware and
Software Resets
460 Description amended.
• Software Reset
15.4.2 Initialization after 460
Hardware Reset
These initial settings must be made while the HCAN2 is in
configuration mode. Deleted Configuration mode is a state in
which the GSR3 bit in GSR is set by a reset.
Figure 15.5 Hardware
Reset Flowchart
461 Amended.
Figure 15.6 Software
Reset Flowchart
462 Amended.
Table 15.5 Setting Range 464
for TSEG1 and TSEG2 in
BCR
Note added.
15.4.2 Initialization after 465 Note added.
Hardware Reset
Mailbox Transmit/Receive
Settings:
Figure 15.8 Transmission 466
Flowchart by Event
Trigger
IMR8=1?
Yes
No
Interrupt to CPU (SLE1)
Clear TXACK
Clear IRR8
Rev. 2.00, 09/04, page 711 of 720