SH7047 Datasheet, PDF (756/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Item
A.2 Register Bits
A.3 Register States in
Each Operating Mode
Page Revisions (See Manual for Details)
681 to
689
Register
IPRK
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
I/O(MMT) I/O(MMT) I/O(MMT) I/O(MMT) —
Bit 2
—
Bit 1
—
Bit 0
—
HCAN2
HCAN2
HCAN2
HCAN2
—
—
—
—
TCSR
OVF
WT/IT
TME
—
—
CKS2
CKS1
CKS0
MSTCR2
—
MSTP14 MSTP13 MSTP12 —
—
MSTP9 —
—
—
MSTP5
MSTP4
MSTP3
MSTP2
—
MSTP0
DTEE
—
—
DTEE5
—
DTEE3
DTEE2
DTEE1
DTEE0
ADTSR
—
—
—
—
TRG1S1 TRG1S0 TRG0S1 TRG0S0
MMT_TMDR —
CKS2
CKS1
CKS0
OLSN
OLSP
MD1
MD0
MCR
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
MCR7
—
MCR5
—
—
MCR2
MCR1
MCR0
HCAN2_BCR TSEG1_3 TSEG1_2 TSEG1_1 TSEG1_0 —
1
—
—
SJW1
SJW0
—
TSEG2_2 TSEG2_1 TSEG2_0
—
—
BSP
IMR
IMR15
IMR14
IMR13
IMR12
—
—
IMR9
IMR8
IMR7
IMR6
IMR5
IMR4
IMR3
IMR2
IMR1
IMR0
REC
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
TEC
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
TXCR1
TXCR31 TXCR30 TXCR29 TXCR28 TXCR27 TXCR26 TXCR25 TXCR24
TXCR23 TXCR22 TXCR21 TXCR20 TXCR19 TXCR18 TXCR17 TXCR16
TXCR0
TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8
TXCR7
TXCR6
TXCR5
TXCR4
TXCR3
TXCR2
TXCR1 —
TCR
TCR15
TCR14
TCR13
TCR12
TCR11
TCR10
TCR9
—
—
—
TPSC5
TPSC4
TPSC3
TPSC2
TPSC1
TPSC0
TSR
—
—
—
—
—
—
—
—
—
—
—
—
—
TSR2
TSR1
TSR0
MB0[5]
—
TCT
—
—
DLC3
DLC2
DLC1
DLC0
MB0[6]
TimeStamp[15:0]
694
Register
Abbrevia
tion
Power-
On
Reset
Manual Hardware Software Module
Reset Standby Standby Standby Sleep
TCSR
Initialized Initialized Initialized Initialized/ —
Held*¹
Held
TCNT
Initialized Initialized Initialized Initialized —
Held
Module
WDT
RSTCSR Initialized Held
/Held*²
Initialized Initialized —
Held
Appendix B Pin States
695 to MCR to TCMR1, MB0[0], and MB0[1] to MB31[18]:
697 Register states in each operating mode are amended.
698 DBGMD:
State in sleep is changed from O to I.
Rev. 2.00, 09/04, page 716 of 720