SH7047 Datasheet, PDF (67/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Table 2.9 Instruction Formats
Instruction Formats
0 format
15
xxxx xxxx xxxx
0
xxxx
n format
15
xxxx nnnn
0
xxxx xxxx
m format
15
xxxx mmmm xxxx
0
xxxx
nm format
15
0
xxxx nnnn mmmm xxxx
Source
Operand

Destination
Operand

Example
NOP

Control register or
system register
Control register or
system register
mmmm: Direct
register
mmmm: Indirect
post-increment
register
mmmm: Indirect
register
mmmm: PC
relative using Rm
mmmm: Direct
register
mmmm: Direct
register
mmmm: Indirect
post-increment
register (multiply-
and-accumulate)
nnnn*: Indirect
post-increment
register (multiply-
and-accumulate)
mmmm: Indirect
post-increment
register
mmmm: Direct
register
mmmm: Direct
register
nnnn: Direct
register
MOVT Rn
nnnn: Direct
register
STS MACH,Rn
nnnn: Indirect pre- STC.L SR,@-Rn
decrement register
Control register or LDC
system register
Rm,SR
Control register or LDC.L @Rm+,SR
system register

JMP @Rm

BRAF Rm
nnnn: Direct
register
nnnn: Indirect
register
MACH, MACL
ADD Rm,Rn
MOV.L Rm,@Rn
MAC.W
@Rm+,@Rn+
nnnn: Direct
register
MOV.L
@Rm+,Rn
nnnn: Indirect pre-
decrement
register
nnnn: Indirect
indexed register
MOV.L Rm,@-
Rn
MOV.L
Rm,@(R0,Rn)
Rev. 2.00, 09/04, page 27 of 720