SH7047 Datasheet, PDF (747/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Item
Page Revisions (See Manual for Details)
11.1 Features
317 Description amended.
• Switchable between watchdog timer mode and interval
timer mode
In watchdog timer mode
• Output WDTOVF signal
If the counter overflows, it is possible to select whether this
LSI is internally reset or not. A power-on reset or manual
reset can be selected as an in internal reset.
In interval timer mode
• If the counter overflows, the WDT generates an interval
timer interrupt (ITI).
• Clears software standby mode
• Selectable from eight counter input clocks.
11.3.3 Reset
321 RSTCSR is an 8-bit readable/writable register that controls the
Control/Status Register
generation of the internal reset signal when TCNT overflows.
(RSTCSR)
Table 12.6 BRR Settings 346
for Various Bit Rates
(Clocked Synchronous
Mode) (1)
Logical Bit Rate (bit/s) n
Operating Frequency Pφ (MHz)
4
10
N
n
N
1000000
0
0*


2500000


0
0*
Table 12.6 BRR Settings 347
for Various Bit Rates
(Clocked Synchronous
Mode) (2)
Logical Bit Rate (bit/s) n
5000000
0
Operating Frequency Pφ (MHz)
20
22
N
n
N
0*


Figure 12.5 Sample SCI 355
Initialization Flowchart
Wait
No
1-bit interval elapsed?
Yes
Set PFC of the external pin used
SCK, TxD, RxD
[4]
12.6.1 Clock
Set RIE, TIE, TEIE, and MPIE bits
[5]
Set TE and RE bits in SCR to 1
< Initialization completion>
Description [4] deleted.
368 ^{Only in reception, the serial clock is continued generating until}
an overrun error is occurred or the RE bit is cleared to 0. To
execute reception in one-character units, select an external
clock as a clock source.
Rev. 2.00, 09/04, page 707 of 720