SH7047 Datasheet, PDF (572/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Register Bit
Initial
Bit Name Value R/W
Description
PDCRL2 2
PDCRL1 2
PD2MD1 0
PD2MD0 0*²
R/W PD2 Mode
R/W Select the function of the PD2/D2/SCK2/AUDATA2
pin.
00: PD2 I/O (port)
01: D2 I/O (BSC)
10: SCK2 I/O (SCI)
11: AUDATA2 I/O (AUD)*¹
PDCRL2 1
PDCRL1 1
PD1MD1 0
PD1MD0 0*²
R/W PD1 Mode
R/W Select the function of the PD1/D1/TXD2/AUDATA1
pin.
00: PD1 I/O (port)
01: D1 I/O (BSC)
10: TXD2 output (SCI)
11: AUDATA1 I/O (AUD)*¹
PDCRL2 0
PDCRL1 0
PD0MD1 0
PD0MD0 0*²
R/W PD0 Mode
R/W Select the function of the PD0/D0/RXD2/AUDATA0
pin.
00: PD0 I/O (port)
10: RXD2 input (SCI)
01: D0 I/O (BSC)
11: AUDATA0 I/O (AUD)*¹
Notes: 1. F-ZTAT only. Setting prohibited for the mask version.
2. The initial value is 1 in the on-chip ROM disabled 8-bit external-expansion mode.
17.1.7 Port E I/O Registers L and H (PEIORL and PEIORH)
The port E I/O registers L and H (PEIORL and PEIORH) are 16-bit readable/writable registers
that are used to set the pins on port E as inputs or outputs. Bits PE21IOR to PE0IOR correspond to
pins PE21 to PE0 (names of multiplexed pins are here given as port names and pin numbers
alone). PEIORL is enabled when the port E pins are functioning as general-purpose inputs/outputs
(PE15 to PD0), TIOC pins are functioning as inputs/outputs of MTU, and SCK2 and SCK3 pins
are functioning as inputs/outputs of SCI. In other states, PEIORL is disabled. PEIORH is enabled
when the port E pins are functioning as general-purpose inputs/outputs (PE21 to PE16) and SCK4
pins are functioning as inputs/outputs of SCI. In other states, PEIORH is disabled.
A given pin on port E will be an output pin if the corresponding PEIORL or PEIORH bit is set to
1, and an input pin if the bit is cleared to 0.
Bits 15 to 6 of PEIORH are reserved. These bits are always read as 0 and should only be written
with 0.
The initial values of PEIORL and PEIORH are H'0000.
Rev. 2.00, 09/04, page 532 of 720