SH7047 Datasheet, PDF (441/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

14.3.2 CMCNT Count Timing
One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) obtained by dividing the peripheral
clock (Pφ) can be selected by the CKS1 and CKS0 bits of CMCSR. Figure 14.3 shows the timing.
Pφ
Internal
clock
CMCNT
input clock
CMCNT
N-1
N
N+1
14.4 Interrupts
Figure 14.3 Count Timing
14.4.1 Interrupt Sources
The CMT has a compare match interrupt for each channel, with independent vector addresses
allocated to each of them. The corresponding interrupt request is output when interrupt request
flag CMF is set to 1 and interrupt enable bit CMIE has also been set to 1.
When activating CPU interrupts by interrupt request, the priority between the channels can be
changed by means of interrupt controller settings. See section 6, Interrupt Controller (INTC), for
details.
The data transfer controller (DTC) can be activated by an interrupt request. In this case, the
priority between channels is fixed. See section 8, Data Transfer Controller (DTC), for details.
14.4.2 Compare Match Flag Set Timing
The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the
CMCOR register and the CMCNT counter match. The compare match signal is generated upon
the final state of the match (timing at which the CMCNT counter matching count value is
updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare
match signal will not be generated until a CMCNT counter input clock occurs. Figure 14.4 shows
the CMF bit set timing.
Rev. 2.00, 09/04, page 401 of 720