SH7047 Datasheet, PDF (752/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Item
Page Revisions (See Manual for Details)
Figure 15.12 Change of 473
Receive Box ID and
Change from Receive Box
to Transmit Box
Amended.
Figure 15.13 HCAN2
474
Sleep Mode Flowchart
Sleep mode clearing method
MCR7 = 1?
No (manual)
Yes (automatic)
MCR5 = 0
Clear sleep mode?
No
15.4.6 HCAN2 Sleep
475
Mode
Figure 15.14 HCAN2 Halt 476
Mode Flowchart
Table 15.6 HCAN2
477
Interrupt Sources
Description added.
Following flow is recommended to enter sleep mode.
1. Set halt mode (MCR1 = 1).
2. Confirm that the HCAN2 is disconnected from the CAN bus
(GSR4 = 1).
3. Clear the source register that controls IRR.
4. Clear halt mode and set bits for sleep mode simultaneously
(MCR1 = 0 and MCR5 = 1).
Amended.
Name
OVR1
Description
Reset processing interrupt by power-on
reset
Overload frame transmission interrupt
Deleted
Rev. 2.00, 09/04, page 712 of 720