SH7047 Datasheet, PDF (754/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Item
Section 20 Mask ROM
Figure 24.1 Mode
Transition Diagram
24.3.2 Software Standby
Mode
Table 25.2 DC
Characteristics
Page
577
605
611
620
Revisions (See Manual for Details)
If you are using the on-chip ROM, select mode 2 or mode 3; if
you are not, select mode 0 or mode 1. The on-chip ROM is
allocated to addresses H'00000000 to H'0001FFFF.
Notes: * NMI and IRQ
Transition to Software Standby Mode:
:
However, the contents of the CPU's internal registers and on-
chip RAM data are retained as long as the specified voltage is
supplied.
Item
Schmitt trigger
input voltage
Symbol
IRQ3 to IRQ0,
POE6 to POE0, TCLKA to TCLKD,
TIOC0A to TIOC0D, TIOC1A, TIOC1B,
TIOC2A, TIOC2B, TIOC3A to TIOC3D,
TIOC4A to TIOC4D
V (V )
T+
IH
V (V )
T– IL
V –V
T+ T–
Table 25.6 Bus Timing
629
Item
Symbol
Min
CS delay time 1
CS delay time 2
WAIT setup time
WAIT hold time
Read data access time
t
CSD1
t
CSD2
t
WTS
t
WTH
t_ACC
—
—
15
0
t_CYC×
(2+n)-35*²*³
Access time from read strobe
t
OE
t×
CYC
(1.5+n)-33*²
Write address setup time
t_AS
0*⁴
Write address hold time
t
WR
5*⁵
Write data hold time
t
WRH
0*⁴
Notes: 1. See page 2 for correspondence of the standard product, wide
temperature-range product, and product model name.
2. n is the number of wait cycles.
3. At the CS assert period extension, t_CYC × (3 + n) - 35.
4. At the CS assert period extension, t .
CYC
5. At the CS assert period extension, 5 + t .
CYC
Rev. 2.00, 09/04, page 714 of 720