SH7047 Datasheet, PDF (466/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value R/W Description
2
IRR2
0
R
Remote Frame Request Interrupt Flag
Status flag indicating that a remote frame has been
received in a mailbox.
[Setting condition]
• When remote frame reception is completed and
corresponding MBIMR = 0
[Clearing condition]
• All bits in the remote request wait register (RFPR) are
cleared
1
IRR1
0
R
Receive Message Interrupt Flag
Status flag indicating that a message has been received
normally in a mailbox.
[Setting condition]
• When data frame reception is completed and
corresponding MBIMR = 0
[Clearing condition]
• All bits in the receive complete register (RXPR) are
cleared
0
IRR0
1
R/W Reset/Halt/Sleep Interrupt Flag
Status flag indicating that the HCAN2 has been reset or
halted and the HCAN2 is now in configuration mode. An
interrupt signal will be generated if the MCR0 (software
reset), MCR1 (halt), or MCR5 (sleep) bit in MCR is set to
1. GSR needs to be read after this bit is set.
1: Transition to software reset mode, halt mode, or sleep
mode
[Clearing condition]
• Writing 1
[Setting condition]
• When processing is completed after software reset
mode (MCR0), halt mode (MCR1), or sleep mode
(MCR5) is requested
Rev. 2.00, 09/04, page 426 of 720