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SH7047 Datasheet, PDF (409/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series
Start initialization
Clear RIE, TIE, TEIE, MPIE,
TE and RE bits in SCR to 0*
Set CKE1 and CKE0 bits in SCR [1]
(TE and RE bits are 0)
Set data transfer format in
[2]
SMR
Set value in BRR
[3]
Wait
No
1-bit interval elapsed?
Yes
Set PFC of the external pin used
SCK, TxD, RxD
[4]
[1] Set the clock selection in SCR.
[2] Set the data transfer format in SMR.
[3] Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4] Set PFC of the external pin used. Set
RxD input during receiving and TxD
output during transmitting. Set SCK
input/output according to contents set
by CKE1 and CKE0.
[5] Wait at least one bit interval, then set
the TE bit or RE bit in SCR to 1.* At this
time, the TxD, RxD, and SCK pins can
be used. The TxD pin is in a mark state
during transmitting. When synchronous
clock output (clock master) is set during
receiving in synchronous mode,
outputting clocks from the SCK pin
starts.
Set RIE, TIE, and TEIE bits
[5]
Set TE and RE bits in SCR to 1
<Transfer start>
Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be
cleared to 0 or set to 1 simultaneously.
Figure 12.15 Sample SCI Initialization Flowchart
12.6.3 Serial data transmission (Clocked Synchronous mode)
Figure 12.16 shows an example of SCI operation for transmission in clocked synchronous mode.
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been
written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty (TXI)
interrupt request is generated. Because the TXI interrupt routine writes the next transmit data
to TDR before transmission of the current transmit data has finished, continuous transmission
can be enabled.
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
mode has been specified and synchronized with the input clock when use of an external clock
has been specified.
Rev. 2.00, 09/04, page 369 of 720