SH7047 Datasheet, PDF (623/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

22.2 Input/Output Pins
Table 22.1 shows the H-UDI pin configuration.
Table 22.1 H-UDI Pins
Pin Name
Test clock
Abbreviation I/O
TCK
Input
Test mode TMS
select
Test data TDI
input
Test data
output
TDO
Test reset TRST
Input
Input
Output
Input
Function
Test clock input
TCK supplies an independent clock to the H-UDI. As
the clock input to TCK is supplied directly to the H-UDI,
a clock waveform with a duty cycle close to 50%
should be input (see section 25, Electrical
Characteristics, for details).
Test mode select input signal
TMS is sampled at the rising edge of TCK. TMS
controls the internal state of the TAP controller.
Serial data input
TDI performs serial input of instructions and data to H-
UDI registers. TDI is sampled at the rising edge of
TCK.
Serial data output
TDO performs serial output of instructions and data
from H-UDI registers. Transfer is synchronized with
TCK. When no signal is being output, TDO goes to the
high-impedance state.
Test reset input signal
TRST is used to initialize the H-UDI asynchronously.
22.3 Register Description
The H-UDI has the following registers. For the register addresses and register states in each
operating mode, refer to appendix A, Internal I/O Register.
• Instruction register (SDIR)
• Status register (SDSR)
• Data register H (SDDRH)
• Data register L (SDDRL)
• Bypass register (SDBPR)
Instructions and data can be input to the instruction register (SDIR) and data register (SDDR) by
serial transfer from the test data input pin (TDI). Data from the status register (SDSR), and SDDR
can be output via the test data output pin (TDO). The bypass register (SDBPR) is a one-bit register
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