SH7047 Datasheet, PDF (196/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

10.3.1 Timer Control Register (TCR)
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each
channel. The MTU has a total of five TCR registers, one for each channel (channel 0 to 4). TCR
register settings should be conducted only when TCNT operation is stopped.
Initial
Bit Bit Name value R/W Description
7
CCLR2 0
R/W Counter Clear 0 to 2
6
CCLR1 0
5
CCLR0 0
R/W These bits select the TCNT counter clearing source. See
R/W ^{tables 10.3 and 10.4 for details.}
4
CKEG1 0
R/W Clock Edge 0 and 1
3
CKEG0 0
R/W These bits select the input clock edge. When the input clock
is counted using both edges, the input clock period is halved
(e.g. Pφ/4 both edges = Pφ/2 rising edge). If phase counting
mode is used on channels 1 and 2, this setting is ignored
and the phase counting mode setting has priority. Internal
clock edge selection is valid when the input clock is Pφ/4 or
slower. When Pφ/1, or the overflow/underflow of another
channel is selected for the input clock, although values can
be written, counter operation compiles with the initial value.
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
[Legend]
X: Don’t care
2
TPSC2 0
R/W Time Prescaler 0 to 2
1
TPSC1 0
0
TPSC0 0
R/W These bits select the TCNT counter clock. The clock source
R/W ^{can be selected independently for each channel. See tables}
10.5 to 10.8 for details.
Rev. 2.00, 09/04, page 156 of 720