SH7047 Datasheet, PDF (425/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value
7
TRGE
0
6
CKS1
0
5
CKS0
0
4
ADST
0
3
ADCS
0
2 to 0 
All 1
R/W Description
R/W Trigger Enable
Enables or disables triggering of A/D conversion by
ADTRG, an MTU trigger, or an MMT trigger.
0: A/D conversion triggering is disabled
1: A/D conversion triggering is enabled
R/W Clock Select 0 and 1
R/W Select the A/D conversion time.
00: Pφ/32
01: Pφ/16
10: Pφ/8
11: Pφ/4
When changing the A/D conversion time, first clear the
ADST bit in the A/D control registers (ADCRs) to 0.
CKS[1,0] = b'11 can be set while Pφ ≤ 25 MHz.
R/W A/D Start
Starts or stops A/D conversion. When this bit is set to 1,
A/D conversion is started. When this bit is cleared to 0,
A/D conversion is stopped and the A/D converter enters
the idle state. In single or single-cycle scan mode, this bit
is automatically cleared to 0 when A/D conversion ends on
the selected single channel. In continuous scan mode, A/D
conversion is continuously performed for the selected
channels in sequence until this bit is cleared by a software,
reset, or in software standby mode, hardware standby
mode, or module standby mode.
R/W A/D Continuous Scan
Selects either single-cycle scan or continuous scan in
scan mode. This bit is valid only when scan mode is
selected.
0: Single-cycle scan
1: Continuous scan
When changing the operating mode, first clear the ADST
bit in the A/D control registers (ADCRs) to 0.
R
Reserved
These bits are always read as 1, and should only be
written with 1.
Rev. 2.00, 09/04, page 385 of 720