SH7047 Datasheet, PDF (483/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

• MBIMR0
Bit Bit Name
15 MBIMR15
14 MBIMR14
13 MBIMR13
12 MBIMR12
11 MBIMR11
10 MBIMR10
9
MBIMR9
8
MBIMR8
7
MBIMR7
6
MBIMR6
5
MBIMR5
4
MBIMR4
3
MBIMR3
2
MBIMR2
1
MBIMR1
0
MBIMR0
Initial Value R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Description
When MBIMRn (n = 0 to 15) is cleared to 0, the
interrupt request in mailbox n is enabled. When set
to 1, the interrupt request is masked.
The interrupt source in a transmit mailbox is TXPRn
(n = 1 to 15) clearing caused by transmission end or
transmission abort. The interrupt source in a receive
mailbox is RXPRn (n = 0 to 15) setting caused by
reception end.
0: Interrupt request in corresponding mailbox is
enabled
1: Interrupt request in corresponding mailbox is
disabled
Rev. 2.00, 09/04, page 443 of 720