SH7047 Datasheet, PDF (510/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

CPU Interrupt Source Settings: CPU interrupt source settings are made in the interrupt mask
register (IMR) and mailbox interrupt register (MBIMR). The message to be received is also
specified. Data frame and remote frame receive wait interrupt requests can be generated for
individual mailboxes in the MBIMR.
Arbitration Field Setting: To receive a message, the message identifier must be set in advance in
the message control (MBx[0] to MBx[5]) for the receiving mailbox. When a message is received,
all the bits in the receive message identifier are compared with those in each message control
register identifier, and if a complete match is found, the message is stored in the matching
mailbox. Mailboxes have a local acceptance filter mask (LAFM) that allows Don't Care settings to
be made. By making the Don't Care setting for all the bits in the receive message identifier,
messages of multiple identifiers can be received.
Examples:
• When the identifier of mailbox 1 is 010_1010_1010 (standard format) and the LAFM setting is
000_0000_0000 (0: Care, 1: Don't care), only one kind of message identifier can be received
by mailbox 1:
Identifier 1: 010_1010_1010
• When the identifier of mailbox 0 is 010_1010_1010 (standard format) and the LAFM setting is
000_0000_0011 (0: Care, 1: Don't care), a total of four kinds of message identifiers can be
received by mailbox 0:
Identifier 1: 010_1010_1000
Identifier 2: 010_1010_1001
Identifier 3: 010_1010_1010
Identifier 4: 010_1010_1011
Message Reception: When a message is received, a CRC check is performed automatically. If the
result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether
the message can be received or not.
• Data frame reception
If the received message is confirmed to be error-free by the CRC check, the identifier of the
receive message and the identifier in the mailbox (including LAFM), are compared. If a
complete match is found, the message is stored in the mailbox. The message identifier
comparison is carried out on each mailbox in turn, starting with mailbox 31 and ending with
mailbox 0. If a complete match is found, the comparison ends at that point, the message is
stored in the matching mailbox, and the corresponding receive complete bit (RXPR0 to
RXPR31) is set in the receive complete register (RXPR). When a message is received, if ID
comparison is carried out and identifiers match in multiple mailboxes (including LAFM), only
the mailbox with the highest mailbox number can receive the message. On receiving a
message, a CPU interrupt request (RM1) may be generated depending on the mailbox interrupt
mask register (MBIMR) and interrupt mask register (IMR) settings.
Rev. 2.00, 09/04, page 470 of 720