SH7047 Datasheet, PDF (565/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

17.1 Register Descriptions
The registers listed below make up the pin function controller (PFC). For details on the addresses
of the registers and their states during each process, see appendix A, Internal I/O Register.
• Port A I/O register L (PAIORL)
• Port A control register L3 (PACRL3)
• Port A control register L2 (PACRL2)
• Port A control register L1 (PACRL1)
• Port B I/O register (PBIOR)
• Port B control register 1 (PBCR1)
• Port B control register 2 (PBCR2)
• Port D I/O register L (PDIORL)
• Port D control register L1 (PDCRL1)
• Port D control register L2 (PDCRL2)
• Port E I/O register H (PEIORH)
• Port E I/O register L (PEIORL)
• Port E control register H (PECRH)
• Port E control register L1 (PECRL1)
• Port E control register L2 (PECRL2)
17.1.1 Port A I/O Register L (PAIORL)
The port A I/O register L (PAIORL) is a 16-bit readable/writable register that is used to set the
pins on port A as inputs or outputs. Bits PA15IOR to PA0IOR correspond to pins PA15 to PA0
(names of multiplexed pins are here given as port names and pin numbers alone). PAIORL is
enabled when the port A pins are functioning as general-purpose inputs/outputs (PA15 to PA0),
SCK2 and SCK3 pins are functioning as inputs/outputs of SCI, and PCIO pins are functioning as
an input/output of MMT. In other states, PAIORL is disabled.
A given pin on port A will be an output pin if the corresponding bit in PAIORL is set to 1, and an
input pin if the bit is cleared to 0.
The initial value of PAIORL is H'0000.
17.1.2 Port A Control Registers L3 to L1 (PACRL3 to PACRL1)
The port A control registers L3 to L1 (PACRL3 to PACRL1) are 16-bit readable/writable registers
that are used to select the functions of the multiplexed pins on port A.
Rev. 2.00, 09/04, page 525 of 720