SH7047 Datasheet, PDF (484/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

15.3.15 Unread Message Status Registers (UMSR1, UMSR0)
UMSR1 and UMSR0 are 16-bit status registers that indicate an unread receive message in a
mailbox is overwritten by a new message. When overwritten by a new message, data in the unread
receive message is lost.
• UMSR1
Bit Bit Name
15 UMSR31
14 UMSR30
13 UMSR29
12 UMSR28
11 UMSR27
10 UMSR26
9
UMSR25
8
UMSR24
7
UMSR23
6
UMSR22
5
UMSR21
4
UMSR20
3
UMSR19
2
UMSR18
1
UMSR17
0
UMSR16
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Unread receive message is overwritten by a new
message
[Setting condition]
• When a new message is received before RXPR
is cleared
[Clearing condition]
• Writing 1
Note: Writing operation by the CPU is valid only for
clearing condition (writing 1) of set status.
Rev. 2.00, 09/04, page 444 of 720