SH7047 Datasheet, PDF (475/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

• TXACK0
Bit Bit Name
15 TXACK15
14 TXACK14
13 TXACK13
12 TXACK12
11 TXACK11
10 TXACK10
9
TXACK9
8
TXACK8
7
TXACK7
6
TXACK6
5
TXACK5
4
TXACK4
3
TXACK3
2
TXACK2
1
TXACK1
0

Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
Description
Status flags that indicate error-free transmission of
the transmit message in the corresponding
mailboxes from 1 to 15. When the message in
mailbox n (n = 1 to 15) has been transmitted error-
free, TXACKn is set to 1.
[Setting condition]
• Completion of message transmission for
corresponding mailbox
[Clearing condition]
• Writing 1
Bit 0 is reserved. This bit is always read as 0. The
write value should always be 0.
Note: Writing operation by the CPU is valid only for
clearing condition (writing 1) of set status.
Rev. 2.00, 09/04, page 435 of 720