SH7047 Datasheet, PDF (312/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

10.7.17 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 10.84 shows the operation timing when there is contention between TCNT write and
overflow.
TCNT write cycle
T1
T2
Pφ
Address
TCNT address
Write signal
TCNT
H'FFFF
TCNT write data
M
TCFV flag
Figure 10.84 Contention between TCNT Write and Overflow
Rev. 2.00, 09/04, page 272 of 720