SH7047 Datasheet, PDF (152/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

8.2.1 DTC Mode Register (DTMR)
DTMR is a 16-bit register that selects the DTC operating mode.
Initial
Bit Bit Name Value
R/W Description
15
SM1
Undefined 
Source Address Mode 1 and 0
14
SM0
Undefined 
These bits specify a DTSAR operation after a data
transfer.
0x: DTSAR is fixed
10: DTSAR is incremented after a transfer
(by +1 when Sz 1 and 0 = 00; by +2 when Sz 1
and 0 = 01; by +4 when Sz 1 and 0 = 10)
11: DTSAR is decremented after a transfer
(by –1 when Sz 1 and 0 = 00; by –2 when Sz 1
and 0 = 01; by –4 when Sz 1 and 0 = 10)
13
DM1
Undefined 
Destination Address Mode 1 and 0
12
DM0
Undefined 
These bits specify a DTDAR operation after a data
transfer.
0x: DTDAR is fixed
10: DTDAR is incremented after a transfer
(by +1 when Sz 1 and 0 = 00; by +2 when Sz 1
and 0 = 01; by +4 when Sz 1 and 0 = 10)
11: DTDAR is decremented after a transfer
(by –1 when Sz 1 and 0 = 00; by –2 when Sz 1
and 0 = 01; by –4 when Sz 1 and 0 = 10)
11
MD1
Undefined 
DTC Mode 1 and 0
10
MD0
Undefined 
These bits specify the DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
9
Sz1
Undefined 
DTC Data Transfer Size 1 and 0
8
Sz0
Undefined 
Specify the size of data to be transferred.
00: Byte-size transfer
01: Word-size transfer
10: longword-size transfer
11: Setting prohibited
Rev. 2.00, 09/04, page 112 of 720