SH7047 Datasheet, PDF (503/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Bit Rate and Bit Timing Settings: The bit rate and bit timing settings are made in the bit
configuration register (BCR). Settings should be made such that all CAN controllers connected to
the CAN bus have the same baud rate and bit width. The 1-bit time consists of the total of the
settable time quanta (TQ). Figure 15.7 shows details of the 1-bit time.
1-bit time (8 to 25 time quanta)
SYNC_SEG
1 time quanta
PRSEG
PHSEG1
Time segment 1 (TSEG1)
4 to 16 time quanta
PHSEG2
Time segment 2
(TSEG2)
2 to 8 time quanta
Figure 15.7 Detailed Description of 1-Bit Time
SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal
bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical
delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This
segment is extended when synchronization (resynchronization) is performed. PHSEG2 is a buffer
segment for correcting phase drift (negative). This segment is shortened when synchronization
(resynchronization) is performed. Limits on the BCR settable values (TSEG1, TSEG2, BRP,
sample point, and SJW) are shown in table 15.4.
Table 15.4 Limits on BCR Settable Values
Name
Abbreviation
Min. Value
Max. Value
Time segment 1
TSEG1
4*³
16
Time segment 2
TSEG2
2*²
8
Baud rate prescaler
BRP
1
256
Bit sample point
BSP
1
3
Re-synchronization jump width
SJW*¹
1
4
Notes: 1. SJW is stipulated in the CAN specifications:
4 ≥ SJW ≥ 1
2. The minimum value of TSEG2 is stipulated in the CAN specifications:
TSEG2 ≥ SJW
3. The minimum value of TSEG1 is stipulated in the CAN specifications:
TSEG1 > TSEG2
Stipulated as: TSEG1 + TSEG2 + 1 = 8 to 25 TQ (Time Quanta)
Rev. 2.00, 09/04, page 463 of 720