SH7047 Datasheet, PDF (305/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

10.7.9 Contention between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 10.77 shows the timing in this case.
Pφ
Address
TGR write cycle
T1 T2
TGR address
Write signal
Input capture
signal
TCNT
M
TGR
M
Figure 10.77 Contention between TGR Write and Input Capture
Rev. 2.00, 09/04, page 265 of 720