SH7047 Datasheet, PDF (520/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

15.8.3 HCAN2 Sleep Mode
The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by CAN bus
operation in HCAN2 sleep mode. Therefore, this flag is not used by the HCAN2 to indicate sleep
mode release. Note that the reset status bit (GSR3) in the general status register (GSR) is set in
HCAN2 sleep mode.
15.8.4 Interrupts
When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8, IRR2, or
IRR1) is not set by reception completion, transmission completion, or transmission cancellation
for the set mailboxes.
15.8.5 Error Counters
In the case of error active and error passive, REC and TEC normally count up and down. In the
bus-off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96
during the count, IRR4 and GSR1 are set, and if REC reaches 128, IRR7 is set.
15.8.6 Register Access
HCAN2 registers except some registers can be accessed only in words. The registers for
mailboxes, MBx[4], MBx[5], and MBx[7] to [14], can be accessed in both bytes and words. The
registers should not be accessed in longwords.
15.8.7 Register in Standby Modes
All HCAN2 registers are initialized in hardware standby mode and software standby mode.
15.8.8 Transmission Cancellation during SOF or Intermission
Setting the contents of TXCR at the SOF or in the intermission state causes a message
transmission and TXACK to be set at the completion of the transmission. However, clearing the
contents of TXCR and TXPR and setting the contents of ABACK are automatically performed.
Despite that both transmission-cancellation and transmission-completion flags are set, incorrect
data will not transmitted.
Rev. 2.00, 09/04, page 480 of 720