SH7047 Datasheet, PDF (652/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Clearing Software Standby Mode: Software standby mode is cleared by the condition below.
• Clearing by the NMI interrupt input
When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit
(NMIE) in ICR1 of the interrupt controller (INTC)) is detected, clock oscillation is started.
This clock pulse is supplied only to the watchdog timer (WDT).
After the elapse of the time set in the clock select bits (CKS2 to CKS0) in TCSR of the WDT
before the transition to software standby mode, the WDT overflow occurs. Since this overflow
indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after
this overflow. Software standby mode is thus cleared and the NMI exception handling is
started.
When clearing software standby mode by the NMI interrupt, set CKS2 to CKS0 bits so that the
WDT overflow period will be longer than the oscillation stabilization time.
When software standby mode is cleared by the falling edge of the NMI pin, the NMI pin
should be high when the CPU enters software standby mode (when the clock pulse stops) and
should be low when the CPU returns from standby mode (when the clock is initiated after the
oscillation stabilization). When software standby mode is cleared by the rising edge of the
NMI pin, the NMI pin should be low when the CPU enters software standby mode (when the
clock pulse stops) and should be high when the CPU returns from software standby mode
(when the clock is initiated after the oscillation stabilization).
• Clearing by the RES pin
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation is started, clock pulse is supplied to the entire chip. Ensure that the RES pin is held
low until clock oscillation stabilizes. When the RES pin is driven high, the CPU starts the reset
exception handling.
• Clearing by the IRQ interrupt input
When the IRQEL bit in the standby control register (SBYCR) is set to 1 and when the falling
edge or rising edge of the IRQ pin (selected by the IRQ3S to IRQ0S bits in ICR1 of the
interrupt controller (INTC) and the IRQ3ES[1:0] to IRQ0ES[1:0] bits in ICR2) is detected,
clock oscillation is started.* This clock pulse is supplied only to the watchdog timer (WDT).
The IRQ interrupt priority level should be higher than the interrupt mask level set in the status
register (SR) of the CPU before the transition to software standby mode.
After the elapse of the time set in the clock select bits (CKS2 to CKS0) in TCSR of the WDT
before the transition to software standby mode, the WDT overflow occurs. Since this overflow
indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after
this overflow. Software standby mode is thus cleared and the IRQ exception handling is
started.
When clearing software standby mode by the IRQ interrupt, set CKS2 to CKS0 bits so that the
WDT overflow period will be longer than the oscillation stabilization time.
Rev. 2.00, 09/04, page 612 of 720