SH7047 Datasheet, PDF (578/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

18.1.1 Register Descriptions
Port A is a 16-bit input/output port. Port A has the following register. For details on register
addresses and register states during each processing, refer to appendix A, Internal I/O Register.
• Port A data register L (PADRL)
18.1.2 Port A Data Register L (PADRL)
The port A data register L (PADRL) is a 16-bit readable/writable register that stores port A data.
Bits PA15DR to PA0DR correspond to pins PA15 to PA0 (multiplexed functions omitted here).
When a pin functions is a general output, if a value is written to PADRL, that value is output
directly from the pin, and if PADRL is read, the register value is returned directly regardless of the
pin state.
When a pin functions is a general input, if PADRL is read, the pin state, not the register value, is
returned directly. If a value is written to PADRL, although that value is written into PADRL, it
does not affect the pin state. Table 18.1 summarizes port A data register L read/write operations.
Bit Bit Name Initial Value R/W Description
15 PA15DR 0
R/W See table 18.1
14 PA14DR 0
R/W
13 PA13DR 0
R/W
12 PA12DR 0
R/W
11 PA11DR 0
R/W
10 PA10DR 0
R/W
9 PA9DR 0
R/W
8 PA8DR 0
R/W
7 PA7DR 0
R/W
6 PA6DR 0
R/W
5 PA5DR 0
R/W
4 PA4DR 0
R/W
3 PA3DR 0
R/W
2 PA2DR 0
R/W
1 PA1DR 0
R/W
0 PA0DR 0
R/W
Rev. 2.00, 09/04, page 538 of 720