SH7047 Datasheet, PDF (300/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

10.7.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented.
Figure 10.72 shows the timing in this case.
TCNT write cycle
T1 T2
Pφ
Address
Write signal
TCNT input
clock
TCNT
TCNT address
N
M
TCNT write data
Figure 10.72 Contention between TCNT Write and Increment Operations
Rev. 2.00, 09/04, page 260 of 720