SH7047 Datasheet, PDF (507/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

CPU Interrupt Source Settings: The CPU interrupt source is set by the interrupt mask register
(IMR) and mailbox interrupt mask register (MBIMR). Transmission acknowledge and
transmission abort acknowledge interrupts can be generated for individual mailboxes in the
mailbox interrupt mask register (MBIMR).
Arbitration Field Setting: The arbitration field is set by message control MBx[0] to MBx[3] in a
transmit mailbox. For a standard format, an 11-bit identifier (STDID[28] to STDID[18]) and the
RTR bit are set, and the IDE bit is cleared to 0. For an extended format, a 29-bit identifier
(STDID[28] to STDID[0], EXTID[17] to EXTID[0]) and the RTR bit are set, and the IDE bit is
set to 1.
Control Field Setting: In the control field, the byte length of the data to be transmitted is set
within the range of zero to eight bytes. The register to be set is the DLC3 to DLC0 bits in the
message control MBx[4] to MBx[5] in a transmit mailbox.
Data Field Setting: In the data field, the data to be transmitted is set within the range zero to eight
bytes. The registers to be set are the message data MSG_DATA_0 to MSG_DATA_7. The byte
length of the data to be transmitted is determined by the data length code (DLC[3:0]) in the control
field. Even if data exceeding the value set in the control field is set in the data field, up to the byte
length set in the control field will actually be transmitted.
Message Transmission: If the corresponding mailbox transmit wait bit in the transmit wait
register (TXPR) is set to 1 after message control and message data have been set, the message
enters the transmit wait state. If the message is transmitted error-free, the corresponding
acknowledge bit in the transmit acknowledge register (TXACK) is set to 1, and the corresponding
transmit wait bit in the transmit wait register (TXPR) is automatically cleared to 0. Also, if the
corresponding bit in the mailbox interrupt mask register (MBIMR) and the mailbox empty
interrupt bit (IMR8) in the interrupt mask register (IMR) are both simultaneously set to enable
interrupts, interrupts (SLE1) may be sent to the CPU.
If transmission of a transmit message is aborted in the following cases, the message is
retransmitted automatically:
• CAN bus arbitration failure (failure to acquire the bus)
• Error during transmission (bit error, stuff error, CRC error, frame error, or ACK error)
Message Transmission Cancellation: Transmission cancellation can be specified for a message
stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the
corresponding mailbox bit to 1 in the transmit wait cancel register (TXCR). Clearing the transmit
wait register (TXPR) does not cancel transmission. When cancellation is executed, the transmit
wait register (TXPR) is automatically reset, and the corresponding bit is set to 1 in the abort
acknowledge register (ABACK). An interrupt to the CPU can be requested. Also, if the
corresponding bit (MBIMR1 to MBIMR31) in the mailbox interrupt mask register (MBIMR) and
Rev. 2.00, 09/04, page 467 of 720